A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. To take advantage of increasing number of devices and to form them into one or more circuits, the various devices need to be interconnected.
To accomplish interconnection on such a small scale, a local interconnect is typically used within an integrated circuit to provide an electrical connection between two or more conducting or semi-conducting regions (e.g., active regions of one or more devices). For example, a plurality of transistors can be connected to form an inverting logical circuit using a local interconnect.
The local interconnect is typically a relatively low-resistance material, such as a conductor or doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of tungsten (W), or a like conductor, which is deposited within an etched opening, such as a via or trench that connects the selected regions together. The use of local interconnects reduces the coupling burden on the subsequently formed higher layers to provide such connectivity, which reduces the overall circuit size and as such tends to increase the circuit's performance. Accordingly, as the density of the circuits increase there is a continuing need for more efficient, effective and precise processes for forming smaller local interconnects.
With this in mind, FIG. 1 depicts a cross-section of a portion 10 of a prior-art semiconductor wafer having a stop layer 22 and a dielectric layer 26 as prepared for local interconnect processing using conventional deposition processes. As shown, portion 10 includes a substrate 12 in which one or more devices have been formed. By way of example, portion 10 includes a gate 16 that is part of a field effect transistor having a source region 13a and a drain region 13b formed within substrate 12, as is known in the art. As shown, gate 16, which is typically a conductive material or a semiconductive material, such as, for example, a doped polycrystalline silicon (referred to hereinafter as polysilicon), is formed on a gate oxide 14 (e.g., silicon dioxide SiO.sub.2) that has been formed on substrate 12. Oxide spacers 20 have been added to the vertical sidewalls 15 of gate 16 and the exposed top surface of gate 16 has an optional conductive silicide 18 formed thereon. Stop layer 22, which is a dielectric material, such as, for example, silicon nitride (e.g., Si.sub.3 N.sub.4), has been deposited over the exposed surfaces of portion 10 using a conventional stop layer deposition process. Dielectric layer 26 has been deposited over stop layer 22 also using a conventional deposition process.
Although stop layer 22 and dielectric layer 26 are both dielectric materials, preferably they are different enough in composition such that subsequent etching processes are capable of etching through dielectric layer 26 while essentially stopping at stop layer 22, thereby avoiding the possibility of etching into substrate 12 and the device regions (e.g., regions 13a-b) formed therein. Without stop layer 22, the etching process would likely extend too far into substrate 12 which could damage existing structures therein and/or cause circuit failures by introducing electrical shorts and other similar problems after the local interconnect has been completed.
Thus, stop layer 22 provides improved process control in the formation of local interconnects which are usually formed using damascene techniques. For example, if dielectric layer 26 is a tetraethlorthosilicate (TEOS) oxide layer and stop layer 22 is a silicon oxynitride (SiO.sub.x N.sub.y) layer, then a subsequent oxide etching process that exhibits a high selectivity to silicon oxynitride can be used to remove selected portions of dielectric layer 26. For example, an octaflourobutene (C.sub.4 F.sub.8) based plasma has a high etch rate for TEOS oxide but a low etch rate for silicon oxynitride.
As depicted in FIG. 1, there is also shown several defects, such as defect 24, that tend to form at the interface between stop layer 22 and dielectric layer 26. Defect 24 is typically created by outgassing effects that occur at the interface during the conventional deposition processes. Defect 24, in certain circumstances, creates topology problems in subsequent layers, such as, dielectric layer 26 that includes a bump 28 above defect 24. In some integrated circuits, defect 24 changes the electrical properties of the various layers, materials, and/or device structures, which affects performance and/or causes the circuit/device to fail during operation. In other circumstances, bump 28 and/or defect 24 present topology problems that hinder or otherwise harm subsequently formed overlying layers, and/or reduce the capabilities of subsequently employed defect inspection techniques/tools to provide an accurate assessment of the fabricated structure.
Thus, as illustrated in FIG. 1, there is a need for methods for reducing or eliminating defects, such as defect 24, during the formation of two or more dielectric layers which are subsequently patterned to form openings for local interconnects.